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1 tm file number 4924 rslic18 is a trademark of intersil corporation. caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil and design is a trademark of intersil corporation. | copyright ?intersil corporation 2000 ISL5586 low power ringing slic for home gateways the rslic18 family of ringing subscriber line interface circuits (rslic) supports analog plain old telephone service (pots) in short and medium loop length, wireless and wireline applications. ideally suited for remote subscriber units, this family of products offers ?xibility to designers with high ringing voltage and low power consumption system requirements. other key features across the product family include: ringing using sinusoidal or trapezoidal waveforms and minimal external discrete application components. the ISL5586 operates up to 100v which translates directly to the amount of ringing voltage supplied to the end subscriber. with the high operating voltage of 100v the rslic18 family can extend subscriber loop lengths to 500 ? (i.e., 5,000 feet) and beyond. the receive and transmit ports of the ISL5586 are designed with differential interfaces to the codec. this implementation provides noise immunity and signal level compatibility with 3.3v codecs. with a few external components, the transmit signal can be biased to within the common mode input range of the codec. the ringing interface of the ISL5586 is dc coupled and has been implemented differentially. the interface allows both ac and dc control of the balanced ringing waveform. features low power consumption differential codec interface telecordia tr-57 compliant software compatible with existing rslic18 designs low idle channel noise programmable transient current limit integrated mtu dc characteristics low external component count silent polarity reversal and on hook transmission thermal shutdown 28 lead surface mount packaging dielectric isolated (di) high voltage design applications cable modems remote subscriber units short loop access platforms voice over internet protocol (voip) voice over dsl (vodsl) broadband wireless access related literature users guide for development board modeling of the ac loop interfacing to dsp codecs (contact factory) technical brief tb363 ?uidelines for handling and processing moisture sensitive surface mount devices (smds) block diagram v rsp v rxm -in v fb f2 f1 f0 ilim rtd det ringing port 4-wire port control logic battery switch transmit sensing detector logic dc control 2-wire port internal loop back pol cdcm v bh v bl bsel transient current limit tip ring tl rd v rsm v rxp v txp v txm v zo cdcp data sheet november 2000
2 pinout ISL5586 (plcc) top view ordering information part number high battery (v bh ) longitudinal balance temp. range o c package package no. 100v 85v 75v 58db 53db ISL5586fcm ?? 0 to 75 28 ld plcc n28.45 ISL5586bim ?? -40 to 85 28 ld plcc n28.45 ISL5586cim ?? -40 to 85 28 ld plcc n28.45 ISL5586dim ?? -40 to 85 28 ld plcc n28.45 device operating modes mode f2 f1 f0 det description low power standby (lps) 0 0 0 shd mtu compliant on hook operating mode. forward active (fa) 0 0 1 shd mtu compliant and oht capable on hook mode, off hook loop feed mode. unused 0 1 0 n/a reserved for internal purposes. reverse active (ra) 0 1 1 shd signalling mode which reverses direction of loop current, otherwise like forward active. ringing 1 0 0 rtd signalling mode used to generate high voltage balanced ringing signal. forward loop back (flb) 1 0 1 shd internal loop back mode which connects internal load across tip and ring terminals. tip open/ground start (to) 1 1 0 shd signalling mode sets tip to high impedance state, ring output still active. power denial (pd) 1 1 1 n/a loop disconnect mode which forces both tip and ring to high impedance. ring i lim rtd cdcm -in v zo v rxm v rxp pol rd v cc tl cdcp v fb bgnd tip f2 v rsm v txp v txm agnd bsel v bl v bh f1 f0 det v rsp 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 19 20 21 22 23 24 25 26 27 28 ISL5586
3 absolute maximum ratings t a = 25 o c thermal information maximum supply voltages v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +7v v cc - v bat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110v esd (human body model) . . . . . . . . . . . . . . . . . . . . . . . . . . 500v maximum tip/ring negative voltage pulse (note 7) . . . . . .v bh -15v maximum tip/ring positive voltage pulse (note 7). . . . . . . . . . + 8v operating conditions temperature range industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c positive power supply (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v negative power supply (v bh , v bl ) . . . . . . . . . . . . . . -100v to -24v thermal resistance (typical, note 1) ja ( o c/w) plcc package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 maximum junction temperature plastic . . . . . . . . . . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (plcc - lead tips only) die characteristics substrate potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -v bh process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bipolar-di caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. ja is measured with the component mounted on a low effective thermal conductivity test board in free air. see tech brief tb379 fo r details. electrical speci?ations unless otherwise speci?d, t a = -40 o c to 85 o c, v bl = -24v, v bh = -100v, v cc = +5v, agnd = bgnd = 0v, loop current limit = 25ma. all ac parameters are speci?d at 600 ? , 2-wire terminating impedance over the frequency band of 300hz to 3.4khz. protection resistors = 0 ? . these parameters apply generically to each product offering. parameter test conditions min typ max units ringing parameters v rsp input impedance (note 2) 35 - - m ? v rsm input impedance (note 2) 10 - - m ? differential ringing gain (note 3) v rs to 2-wire, r load = 5 ren - 99.5 - v/v ringing voltage total distortion r l = 1.3 k ? , v t-r = |v bh | -5 - 0.8 5 % 4-wire to 2-wire ringing off isolation forward active mode, referenced to v rs input. - 100 - db 2-wire to 4-wire transmit isolation ringing mode referenced to the differential ringing amplitude. - 100 - db centering voltage accuracy tip, referenced to v bh /2 + 0.5v -3.0 0.2 3.0 v ring, referenced to v bh/2 + 0.5v -3.0 0.2 3.0 v ac transmission parameters receive input impedance, v rxp (note 2) 379 541 - k ? receive input impedance, v rxm (note 2) 100 142 - k ? transmit output impedance (note 2) dc - 0.01 - ? transmit output drive capability (note 2) current 0.30 1.0 - ma capacitance to ground - 1.0 100 pf 4-wire port overload level thd = 1% 3.1 3.5 - v peak 2-wire port overload level thd = 1% 3.1 3.5 - v peak 2-wire return loss (note 2) 200hz f 1khz - 35 - db 1khz f 3.4khz - 23 - db longitudinal current capability per wire (note 2) false detect 20 - - ma rms false detect in low power standby 10 - - ma rms 2-wire longitudinal balance (on-hook and off-hook) (notes 4, 5) 200hz, 500hz, 1000hz 58 61 - db 3000hz 53 61 - db 4-wire longitudinal balance (on-hook and off-hook) (notes 4, 5) 200hz, 500hz, 1000hz 58 64 - db 3000hz 53 62 - db 4-wire to 2-wire insertion loss 0dbmo at 1khz 2.72 2.92 3.12 db 2-wire to 4-wire insertion loss 0dbmo at 1khz -0.2 0 0.2 db 4-wire to 4-wire insertion loss 0dbmo at 1khz 2.72 2.92 3.12 db frequency response, on hook, 2-wire to 4-wire, 4-wire to 2-wire, 4-wire to 4-wire referenced to 0dbmo at 1004hz, 400hz f 2800hz -0.15 0.03 0.15 db frequency response, off hook 2-wire to 4-wire, 4-wire to 2-wire, 4-wire to 4-wire referenced to 0dbmo at 1004hz, f = 400hz, 2800hz -0.15 0.03 .15 db ISL5586
4 amplitude tracking, off hook, 2-wire to 4-wire, 4-wire to 2-wire, 4-wire to 4-wire +3dbmo to -37dbmo, f = 1004hz, referenced to 0dbmo - 0.02 - db -37 to -50dbmo - 0.05 - db -50 to -55dbmo - 0.10 - db amplitude tracking, on-hook 0dbmo to -37dbmo, f = 1004hz, referenced to 0dbmo - 0.01 - db signal to distortion, 2-wire to 4-wire, 4-wire to 2-wire, 4-wire to 4-wire, on-hook and off-hook input level 0dbmo to -30dbmo 33 45 - db input level -30 to -40dbmo 27 40 - db input level -40 to -45dbmo 22 29 - db signal frequency distortion (0hz to 12khz) 0dbmo input, 0 hz f 12khz 28 45 - db single frequency distortion (0hz to 4khz) 0dbmo input, 1004hz f 1024hz 40 50 - db intermodulation distortion, 2-wire to 4-wire, 4-wire to 2-wire, 4-wire to 4-wire (ieee standard 743-1984) 4-tone second-order intermodulation products 43 50 - db 4-tone third-order intermodulation products 44 62 - db idle channel noise, 2-wire (note 5) c-message, forward active, low battery enabled - 10.0 13.0 dbrnc idle channel noise, 4-wire (note 5) c-message, forward active, low battery enabled - 10.0 13.0 dbrnc dc parameters off-hook loop current limit programming accuracy (1% external resistor) -8.5 1.0 +8.5 % programming range 15 - 45 ma off-hook transient current limit programming accuracy -10 - +10 % programming range 40 - 100 ma loop current during low power standby forward polarity only (r l = 600 ? ) - 24 - ma open circuit voltage (|tip - ring|) forward and reverse active modes v bl = -16v - 7.0 - v dc v bl = -24v 13.5 14.5 16.5 v dc v bh > -60v 43 48 - v dc open circuit voltage (|tip-ring|) lps v bh > -60v 43 51 - v dc absolute open circuit voltage (relative to gnd) v rg in fa, v tg in ra, v bh > -60v - -53 -56 v dc absolute open circuit voltage v rg in lps - -52 -56 v dc test access functions loopback max battery - - 52 v loop detectors and supervisory functions switch hook programming range 5 - 15 ma switch hook programming accuracy assumes 1% external programming resistor -10 - +10 % dial pulse distortion - 1.0 - % ring trip comparator threshold 2.3 2.60 2.9 v ring trip programming current accuracy -10 - +10 % thermal shutdown threshold ic junction temperature - 175 - o c logic inputs (f0, f1, f2, bsel) input low voltage - - 0.8 v input high voltage 2.0 - - v input low current (f0, f1, f2) v il = 0.4v - 7.5 20 a input low current (bsel) v il = 0.4v - 1.0 - a input high current (f0, f1, f2, bsel) v ih = 2.4v - 0.01 - a logic output ( det) output low voltage i ol = 5ma - 0.15 0.4 v output high voltage i oh = 100 a 2.4 3.2 3.5 v supply currents low power standby, bsel = 2.0v, v bh = -75v to -100v i cc - 3.2 5.0 ma i bh - 0.65 0.9 ma forward or reverse , bsel =.8v i cc - 5.0 6.5 ma i bl - 1.5 2.5 ma electrical speci?ations unless otherwise speci?d, t a = -40 o c to 85 o c, v bl = -24v, v bh = -100v, v cc = +5v, agnd = bgnd = 0v, loop current limit = 25ma. all ac parameters are speci?d at 600 ? , 2-wire terminating impedance over the frequency band of 300hz to 3.4khz. protection resistors = 0 ? . these parameters apply generically to each product offering. (continued) parameter test conditions min typ max units ISL5586
5 forward active, bsel = 2.0v, v bh = -100v i cc - 7.0 9.0 ma i bl - 1.4 2.0 ma i bh - 1.8 3.0 ma forward active, bsel = 2.0v, v bh = -85v i cc - 6.6 8.5 ma i bl - 1.35 2.0 ma i bh - 1.60 2.75 ma forward active, bsel = 2.0v, v bh = -75v i cc - 6.3 8.0 ma i bl - 1.25 2.0 ma i bh - 1.45 2.5 ma ringing, bsel = 2.0v, v bh = -100v i cc - 7.4 10.0 ma i bl - 1.5 2.0 ma i bh - 2.2 3.0 ma ringing, bsel = 2.0v, v bh = -85v i cc - 6.80 9.25 ma i bl - 1.36 2.0 ma i bh - 2.1 3.0 ma ringing, bsel = 2.0v, v bh = -75v i cc - 6.4 8.5 ma i bl - 1.26 2.0 ma i bh - 2.0 3.0 ma forward loopback, bsel = 0.8v, v bl = -24v i cc - 10.3 13.5 ma i bl - 23.0 32.0 ma tip open, bsel = 2.0v i cc - 3.2 - ma i bl - 0.1 - ma power denial, bsel = 0.8v or 2.0v i cc - 3.4 6.0 ma i bl - 0.22 0.50 ma on hook power dissipation (note 6) forward or reverse v bl = -24v - 57 - mw low power standby v bh = -100v - 83 - mw v bh = -85v - 70 - mw v bh = -75v - 64 - mw ringing v bh = -100v - 294 - mw v bh = -85v - 236 - mw v bh = -75v - 206 - mw off hook power dissipation (note 6) forward or reverse v bl = -24v, i lim = 25ma, r l = 300 ? - 305 - mw power supply rejection ratio v cc to 2-wire, bsel = 0.8v f = 50khz - 50 - db f = 300hz f 3400hz - 45 - db f = 8khz f 16khz - 28 - db v cc to 4-wire, bsel = 0.8v f = 50hz - 70 - db f = 300hz f 3400hz - 55 - db f = 8khz f 16khz - 40 - db v bl to 2-wire, bsel = 0.8v f = 50hz - 25 - db f = 300hz f 3400hz - 38 - db f = 8khz f 16khz - 28 - db v bl to 4-wire, bsel = 0.8v f = 50hz - 27 - db f = 300hz f 3400hz - 36 - db f = 8khz f 16khz - 23 - db v bh to 2-wire, bsel = 2.0v f = 50hz - 27 - db f = 300hz f 3400hz - 35 - db f = 8khz f 16khz - 23 - db electrical speci?ations unless otherwise speci?d, t a = -40 o c to 85 o c, v bl = -24v, v bh = -100v, v cc = +5v, agnd = bgnd = 0v, loop current limit = 25ma. all ac parameters are speci?d at 600 ? , 2-wire terminating impedance over the frequency band of 300hz to 3.4khz. protection resistors = 0 ? . these parameters apply generically to each product offering. (continued) parameter test conditions min typ max units ISL5586
6 design equations refer to figure 14 for programming resistor connections. loop supervision thresholds switch hook detect the desired switch hook detect threshold current (i sh ) is set by a single external resistor, r sh as follows the loop current threshold programming range is from 5ma to 15ma. ring trip detect the ring trip detect threshold (i rt ) is set by a single external resistor, r rt as follows. i rt should be set between the peak ringing current and the peak off hook current while still ringing. in addition, the ring trip current must be set below the transient current limit including tolerances. the ringing signal ?ter capacitor c rt , in parallel with r rt sets the ring trip response time. loop current limit the dc loop current limit (i lim ) is programmed by the external resistor r il as follows. the loop current limit programming range is from 15ma to 45ma. impedance matching the ac source impedance of the slic is programmed with the external impedance network z s as described next. to synthesize and match resistive line terminations the programming network is simply a resistor (r s ) as shown in figure 14. for complex line terminations such as the one illustrated in figure 1, a complex programming network is required. resistive impedance synthesis the ac source resistance of the slic is synthesized with a single external resistor r s as follows: the synthesized resistance (z 0 ) is determined by the characteristic line resistance and protection resistors as shown in equation 5. complex impedance synthesis a complex network is used in place of r s when the termination impedance of the line is complex as shown in figure 1. the component r s has a different design equation than the r s used for resistive impedance synthesis. the design equations for each component are provided below where rp1 and rp2 are the protection resistors and r p is a component of the programming network. v bh to 4-wire, bsel = 2.0v f = 50hz - 76 - db f = 300hz f 3400hz - 55 - db f = 8khz f 16khz - 42 - db notes: 2. these parameters are controlled via design and statistical process control and are not directly tested. these parameters are characterized upon initial design release and upon design changes which would affect these characteristics. 3. input voltage = 0.636v rms for v bh = -100v, 0.530v rms for v bh = -85v and 0.460v rms for -75v devices. 4. tested per ieee455-1985, with 368 ? resistors connected to the tip and ring terminals. 5. these parameters are tested 100% at room temperature, and are guaranteed but not tested across the full temperature range via statistical characterization and design. 6. the power dissipation is based on actual device measurements and will be less than worst case calculations based on data sheet supply current limits . 7. characterized with 2 x 10us and 10 x 1000us first level lightning surge waveform (gr-1089-core). electrical speci?ations unless otherwise speci?d, t a = -40 o c to 85 o c, v bl = -24v, v bh = -100v, v cc = +5v, agnd = bgnd = 0v, loop current limit = 25ma. all ac parameters are speci?d at 600 ? , 2-wire terminating impedance over the frequency band of 300hz to 3.4khz. protection resistors = 0 ? . these parameters apply generically to each product offering. (continued) parameter test conditions min typ max units r sh 615 i sh ? = (eq. 1) r rt 1800 i rt ? = (eq. 2) r il 1760 i lim ------------ - = (eq. 3) r s z 0 400 3 --------- - ?? ?? 133.3 z 0 () == (eq. 4) z o r l rp 1 rp 2 + () = (eq. 5) figure 1. complex programming network 2-wire termination impedance (z l ) r 1 r 2 c 2 programming network (z s ) r s r p c p r s 133.3 r1 rp 1 rp 2 () = (eq. 6) r p 133.3 r 2 = (eq. 7) ISL5586
7 4-wire to 2-wire gain the 4-wire to 2-wire gain (g 42 ) is de?ed as the receive gain. it is a function of the terminating impedance, synthesized impedance and protection resistors. the gain is de?ed from the receive input terminals (v rxp , v rxm ) to the terminating impedance (z l ) on the 2-wire side, and is illustrated in figure 12. when the device source impedance and the protection resistors equal the terminating impedance, the receive gain equals 2.92db and is inverted with respect to the input. 2-wire to 4-wire gain the 2-wire to 4-wire gain (g 24 ) is the gain from tip and ring to the transmit differential output. the transmit gain is given by equation 11. note that v tr is defined on the line side of the protection resistors (reference figure 13). with z l set to 600 ohms, the protection resistors set to 50 ? /terminal and z 0 =z l -2rp the transmit gain equals -0.833 (-1.59db) and is inverted with respect to the 2-wire input (v tr ). transhybrid gain the transhybrid gain is de?ed as the 4-wire to 4-wire gain (g 44 ) and is given by equation 12 (reference figure 14)). transient current limit the drive current capability of the output ampli?rs is determined by an externally programmable output current limit circuit which is separate from the dc loop current limit function. the transient current limit is programmed with a resistor to ground at the tl pin. the current limit circuit works in both the source and sink direction, with an internally ?ed offset to prevent the current limit functions from turning on simultaneously. the current limit function is provided by sensing line current and reducing the voltage drive to the load when the externally set threshold is exceeded, hence forcing a constant source or sink current. source current programming the source current is externally programmed as shown in equation 13. for example, a source current limit setting of 50ma is programmed with a 35.6k ? resistor connected from pin 16 of the device to ground. this setting determines the maximum amount of current which flows from tip to ring during an off hook event until the dc loop current limit responds. in addition this setting also determines the amount of current which will flow from tip or ring when external battery faults occur. sink current programming the sink current limit is internally offset 20% higher than the externally programmed source current limit setting. if the source current limit is set to 50ma, the sink current limit will be 60ma. this setting will determine the amount of current which flows into tip or ring when external ground faults occur. functional description each ampli?r is designed to limit source current and sink current. the diagram below shows the functionality of the circuit for the case of limiting the source current. a similar diagram applies to the sink current limit with current polarity changed accordingly. during normal operation, the error current (i err ) is zero and the output voltage is determined by the signal current (i sig ) multiplied by the 200k feedback resistor. with the current polarity as shown for i sig , the output voltage moves positive with respect to half battery. assuming the ampli?r output is driving a load at a more negative potential, the ampli?r output will source current. during excessive output source current ?w, the scaled output current (i o /k) exceeds the reference current (i ref ) forcing an error current (i err ). with the polarity as shown the error current subtracts from the signal current, which reduces the ampli?r output voltage. by reducing the output voltage the source current to the load is decreased and the output current is limited. determining the proper setting since this feature programs the maximum output current of the device, the setting must be high enough to allow for detection of ring trip or programmed off hook loop current, whichever is greater. c p c 2 133.3 ? = (eq. 8) z o r1 rp1 rp2 () r2 c2 + = (eq. 9) g 42 2.8 z l z o +2r p +z l ----------------------------------------- - ?? ?? ?? = (eq. 10) g 24 2 z o z o +2r p +z l ----------------------------------------- - ?? ?? ?? = (eq. 11) g 44 2.8 z o z o 2r p z l ++ -------------------------------------- - ?? ?? ?? = (eq. 12) r tl 1780 i src ------------- = (eq. 13) i snk 1.20 i src = (eq. 14) figure 2. current limit functional diagram tip or ring + - i ref = 1.21/tl i o i o /k i err i sig 20 200k vb/2 ISL5586
8 to allow for proper ring trip operation, the transient current limit setting should be set at least 25% higher than the peak ring trip current setting. setting the transient current 25% higher should account for programming tolerances of both the ring trip threshold and the transient current limit. if loop current is larger than ring trip current (low ren applications) then the transient current limit should be set at least 35% higher than the loop current setting. the slightly higher offset accounts for the slope of the loop current limit function. attention to detail should be exercised when programming the transient current limit setting. if ring trip detect does not occur while ringing, then re-examine the transient current limit and ring trip threshold settings. low power standby mode overview the low power standby mode (lps, 000) should be used in conjunction with the high battery during idle line conditions. the slic is designed to operate from the high battery during this mode so mtu compliance can be met. most of the internal circuitry is powered down, resulting in low power dissipation. if mtu compliance is not required during idle line conditions, the device may be operated from the low battery which will decrease the standby power dissipation. 2-wire interface in the lps mode, the 2-wire interface is maintained with internal switches, resistors, and voltage references. the tip and ring amplifiers are turned off to conserve power. the device will provide mtu compliance, loop current, and loop supervision. figure 2 represents the internal circuitry providing the 2-wire interface when in this mode of operation. mtu compliance maintenance termination unit or mtu compliance places dc voltage requirements on the 2-wire terminals during idle line conditions. the minimum idle voltage for compliance is 42.75v. the high side of the mtu range is 56v. the voltage is expressed as the difference between tip and ring. the tip voltage is held near ground through a 600 ? resistor and switch. the ring voltage is nominally limited to -49v by the mtu reference. a switch and 600 ? resistor connect the mtu reference to the ring terminal. when the high battery voltage exceeds the mtu reference of -49v, the ring terminal will be clamped by the internal reference. the same ring relationships apply when operating from the low battery. for operating battery voltages (v bh ) less than or equal to the internal mtu reference, the ring voltage will be approximately 4.5 volts more positive than v bh . loop current in the lps mode, the device is capable of providing dc current to a load through a path of resistors and switches. the current available for switch hook detect is a function of the off hook loop resistance (r loop ). this includes the off hook phone resistance and copper loop resistance. the current available during lps is given by equation 15. internal current limiting of the standby switches will limit the maximum current to approximately 23ma. the longitudinal current capability is guaranteed to be greater than or equal to 10ma rms per pin. when longitudinal currents exceed this level, false off hook detection may occur. the reduction in longitudinal current capability with respect to the forward active mode is a result of turning off the tip and ring amplifiers. on hook power dissipation the on hook power dissipation of the slic in the lps mode is determined by the operating voltages and quiescent currents and is calculated below. table 1. device interfaces during lps interface on off notes receive - x ac transmission, impedance matching and ringing are disabled during this mode. ringing - x transmit - x 2-wire x - amplifiers disabled. loop detect x - switch hook. figure 3. lps 2-wire interface circuit diagram tip amp ring amp tip ring mtu ref gnd 600 ? 600 ? i loop 1 49 () () 600 600 r loop ++ () ? = (eq. 15) p lps v bh i bhq v bl i blq v cc i ccq ++ = (eq. 16) ISL5586
9 the quiescent current terms are speci?d in the electrical tables for each operating mode. load power dissipation is not a factor since this is an on hook mode. some applications may specify a standby current. the standby current may be a charging current required for modern telephone electronics. standby current power dissipation any standby line current, i slc , introduces an additional power dissipation term p slc . equation 17 illustrates the power contribution is zero when the standby line current is zero. if the battery voltage is less than -49v (the mtu clamp is off), the standby line current power contribution reduces to equation 18. most applications do not specify charging current requirements during standby. when speci?d, the typical charging current may be as high as 5ma . forward active mode overview the forward active mode (fa, 001) is the primary ac transmission mode of the slic. on hook transmission, dc loop feed and voice transmission are supported during this mode. the device may be operated from either high or low battery for on-hook transmission and from low battery for loop feed. loop supervision is provided by the switch hook detector at the det output. when det goes low, the low battery should be selected for dc loop feed and voice transmission. on-hook transmission the primary purpose of on hook transmission will be to support caller id and other advanced signalling features. the transmission over load level while on hook is 3.1v peak . when operating from the high battery, the dc voltages at tip and ring are mtu compliant. the typical tip voltage is -4v and the ring voltage is a function of the battery voltage for battery voltages less than -60v as shown in equation 19. feed architecture the slic design implements a voltage feed current sense architecture. the voltage across tip and ring is controlled by sensing the load current. resistors are placed in series with the tip and ring outputs to provide the current sensing function. the diagram below illustrates the concept. by monitoring the current at the ampli?r outputs, a negative feedback mechanism sets the output voltage for a de?ed load. the ampli?r closed loop gains are set by internal resistor ratios (r a , r b , r c ) providing all the performance bene?s of matched resistors. the internal sense resistor r cs , is much smaller than the gain resistors and are typically 20 ? . the feedback mechanism, k s , represents the gain con?uration providing negative feedback to the loop. dc loop feed the feedback mechanism for monitoring the dc portion of the loop current is contained within the loop detector block. a low pass ?ter is used in the feedback loop to block voice and other signals from interfering with the loop current limit function. the pole of the low pass ?ter is set by the external 4.7 f capacitor (c dc) and an internal 8k ? resistor. the dc feed characteristic of the slic will drive tip and ring towards half battery to regulate the dc loop current. for light loads, tip will be near -4v and ring will be near v vbl + 4.5v. most applications will operate the device from low battery while off hook. the following diagram depicts the dc feed characteristic. the point on the y-axis labeled v tr(oc) is the open circuit tip to ring voltage and is de?ed by the feed battery voltage. the curve of figure 5 shows the loop current for a given set of loop conditions. the loop conditions are determined by the low battery voltage and the dc loop resistance. the dc loop resistance is the sum of the protection resistance, copper resistance (ohms/foot) and the telephone off hook dc resistance. p slc i slc v bh 49 1i slc x1200 ++ () = (eq. 17) p slc i slc v bh 1i slc x1200 ++ () = (eq. 18) v ring v bh 4.5v + = (eq. 19) figure 4. voltage feed current sense diagram + - + - v in v out r c r cs r l r b r a k s figure 5. dc feed characteristic m = ( ? v tr / ? i l ) = 11.1k ? i loop (ma) i lim v tr(oc) v tr , dc (v) v tr oc () v bl 9 = (eq. 20) ISL5586
10 the slope of the feed characteristic and the battery voltage de?e the maximum loop current on the shortest possible loop as the short circuit current i sc . the term i lim is the programmed current limit, 1760/r il . the line segment i a represents the constant current region of the loop current limit function. the maximum loop resistance for a programmed loop current is de?ed as r knee . when r knee is exceeded, the device will transition from constant current feed to constant voltage, resistive feed. the line segment i b represents the resistive feed portion of the load characteristic. power dissipation the power dissipated by the slic in the forward active mode while on hook is strictly a function of the quiescent currents for each supply. off hook power dissipation is increased above the quiescent power dissipation by the dc load. if the loop length is less than or equal to r knee , the device is providing constant current (i a) , and the power dissipation is calculated using equation 26. if the loop length is greater than r knee , the device is operating in the constant voltage, resistive feed region. the power dissipated in this region is calculated using equation 27. since the current relationships are different for constant current versus constant voltage, the region of device operation is critical to valid power dissipation calculations. reverse active mode overview the reverse active mode (ra, 011) provides the same functionality as the forward active mode. on hook transmission, dc loop feed, and voice transmission are supported. loop supervision is provided by the switch hook detector. the device may be operated from either high or low battery. when in the reverse active mode the tip and ring dc voltage characteristics exchange roles. that is, ring is typically 4v below ground and tip is typically 4.5v more positive than battery. silent polarity reversal changing from forward active to reverse active or vice versa is referred to as polarity reversal. many applications require control of the polarity reversal transition time. requirements range from minimizing cross talk to protocol signalling. the slic uses an external low voltage capacitor, c pol , to set the reversal time. the capacitor is isolated from the ac loop so that loop stability is not in?enced by its selection. once c pol is set, the reversal time will remain nearly constant over various load conditions. the internal circuitry used to set the polarity reversal time is shown in figure 7. during forward active the switch is open and the current from source i1 charges the external timing capacitor c pol . the internal resistor provides a clamping function for the voltage at the pol node. when the reverse active mode is initiated the switch closes and the difference current (i2-i1) discharges the timing capacitor. the voltage at the pol node drives one side of a transistor differential pair which forces the forward or reverse condition on the tip and ring amplifiers. the forward/reverse transition time is given by equation 28, where ? time is the required reversal time. polarized capacitors may be used for c pol . the low voltage at the pol pin and minimal voltage excursion in the order of 0.75v, are well suited for polarized capacitors. figure 6. i loop versus r loop load characteristic r loop (? ) r knee i lim i loop (ma) i sc i a i b 2r p i sc i lim v tr oc () 2r p i lim 1.1e4 ----------------------------------------------------- - + = (eq. 21) i a i lim v tr oc () r loop i lim 1.1e4 -------------------------------------------------------------- + = (eq. 22) r knee v tr oc () i lim ------------------------ = (eq. 23) i b v tr oc () r loop ------------------------ = (eq. 24) p faq v bh i bhq v bl i blq v cc i ccq ++ = (eq. 25) p fa ia () p fa q () v bl xi a () r loop xi 2 a () + = (eq. 26) p fa ib () p fa q () v bl xi b () r loop xi 2 b () + = (eq. 27) c pol ? time 75000 ---------------- = (eq. 28) ISL5586
11 power dissipation the power dissipation equations for forward active operation also apply to the reverse active mode. ringing overview the ringing mode (rng, 100) provides linear ampli?ation to support a variety of ringing waveforms. a programmable ring trip function provides loop supervision and auto disconnect upon ring trip. the device is designed to operate from the high battery during this mode. architecture the slic provides linear ampli?ation to the differential signal applied to the ringing inputs (v rsp , v rsm ). the differential ringing gain of the device is 100v/v. the circuit model for the ringing path is shown in figure 8. the voltage gain from the differential ringing input to the tip output is 50v/v. the resistor ratios provide a gain of 10 and the current mirror provides a gain of 5. the voltage gain from the differential input to the ring output is -50v/v. the equations for the tip and ring outputs during ringing are provided below. when the differential input signal is zero, the tip and ring ampli?r outputs are centered at half battery. the device provides auto centering for easy implementation of sinusoidal ringing waveforms. both ac and dc control of the tip and ring outputs is available during ringing. this feature allows for dc offsets as part of the ringing waveform. ringing input terminals the differential terminals feature high input impedance which allows the use of low value capacitors for ac coupling the ring signal if necessary. the ringing input is enabled only during the ringing mode, therefore a free running oscillator may be connected at all times. when operating from a battery of -100v, each ampli?r, tip and ring, will swing a maximum of 95v p-p . hence, the maximum differential signal swing between v rsp and v rsm to achieve full scale ringing is approximately 1.9v p-p . logic control ringing patterns consist of silent and ringing intervals. the ringing to silent pattern is called the ringing cadence. during the silent portion of ringing, the device can be programmed to any other operating mode. the most likely candidates are low power standby or forward active. depending on system requirements, the low or high battery may be selected. loop supervision is provided with the ring trip detector. the ring trip detector senses the change in loop current when the phone is taken off hook. the loop detector full-wave rectifies the ringing current, which is then filtered with external components r rt and c rt . the resistor r rt sets the trip threshold and the capacitor c rt sets the trip response time. most applications will require a trip response time less than 150ms. three very distinct actions occur when the device detects a ring trip. first, the det output is latched low. the latching mechanism eliminates the need for software ?tering of the detector output. the latch is cleared when the operating mode is changed externally. second, the ringing inputs are disabled, removing the ring signal from the line. third, the device is internally forced to the forward active mode. power dissipation the power dissipation during ringing is dictated mostly by the load driving requirements and the ringing waveform. the key to valid power calculations is the correct definition of average and rms currents. the average current defines the high battery supply current. the rms current defines the load current. the cadence provides a time averaging reduction in the peak power. the total power dissipation consists of ringing power, p r , and the silent interval power, p s . figure 7. reversal timing control c pol pol i 1 75k ? i 2 figure 8. linear ringing model tip ring r/8 r r + - + - 5:1 20 20 + - v bh 2 + - + - + - v rsp v rsm r r 1.25r 1.25r v t v bh 2 ----------- 50 v dif () + = (eq. 29) v r v bh 2 ----------- 50 v dif () = (eq. 30) p rng p r t r t r t s + -------------- p s t s t r t s + -------------- + = (eq. 31) ISL5586
12 the terms t r and t s represent the cadence. the ringing interval is t r and the silent interval is t s . a typical cadence ratio t r :t s is 1:2. the quiescent power of the device in the ringing mode is de?ed in equation 32. the total power during the ringing interval is the sum of the quiescent power and loading power: for sinusoidal waveforms, the average current, i avg , is de?ed in equation 34. the silent interval power dissipation will be determined by the quiescent power of the selected operating mode. forward loop back mode overview the forward loop back mode (flb, 101) provides test capability for the slic. an internal signal path is enabled allowing for both dc and ac veri?ation by the connection of an internal 600 ohm resistor across tip and ring. this internal terminating resistor has a tolerance of 10% at room temperature. the device is intended to operate from only the low battery during this mode. architecture when the forward loop back mode is initiated internal switches connect a 600 ? load across the outputs of the tip and ring ampli?rs as shown below. dc veri?ation when the internal signal path is provided, dc current will ?w from tip to ring. the dc current will force det low, indicating the presence of loop current. in addition to verifying device functionality, toggling the logic output veri?s the interface to the system controller. ac veri?ation the entire ac loop of the device is active during the forward loop back mode. therefore a 4-wire to 4-wire level test capability is provided. depending on the transhybrid balance implementation, test coverage is provided by a one or two step process. system architectures which cannot disable the transhybrid function would require a two step process. the ?st step would be to send a test tone to the device while on hook and not in forward loop back mode. the return signal amplitude would be the test signal amplitude times the gain of the transhybrid ampli?r. since the device would not be terminated in the on hook mode, cancellation would not occur. the second step would be to program the device to flb mode and resend the test tone. the return signal would be much lower in amplitude than the ?st step, indicating the device was active and the internal termination attenuated the return signal. system architectures which can disable the transhybrid function would achieve test coverage with a signal step. once the transhybrid function is disabled the slic can be programmed to the flb mode and the test tone can be sent. the return signal level is determined by the 4-wire to 4-wire gain of the slic times the amplitude of the signal sent. tip open/ground start mode overview the tip open mode (to, 110) is intended for compatibility with pbx type interfaces. the device does not provide transmission capability in this mode which is intended for idle line conditions. loop supervision is provided by the switch hook detector and either high or low battery operation is supported. functionality during tip open operation, the tip switch is disabled and the ring switch is enabled. the minimum tip impedance is 30k ? . the only active path through the device will be through the ring switch. in keeping with the mtu characteristics of the device, ring will not exceed -56v when operating from the high battery. though mtu does not apply to tip open, safety requirements are satis?d. p rq () v bh i bhq v bl i blq v cc i ccq ++ = (eq. 32) p r p rq () v bh i avg v rms 2 z ren r loop + ------------------------------------------ + = (eq. 33) i avg 2 -- - ?? ?? v rms 2 z ren r loop + ------------------------------------------ = (eq. 34) figure 9. forward loop back internal termination ring amp tip amp ring tip 600 ? ISL5586
13 power denial overview the power denial mode (111) will shutdown the entire device except for the logic interface. loop supervision is not provided. this mode may be used as a sleep mode or to shut down the slic in the presence of fault conditions. switching between high and low battery will have no effect during power denial. functionality during power denial, both the tip and ring ampli?rs are disabled, presenting high impedances to the line. the voltages at both outputs are near ground. thermal shutdown in the event the safe die temperature is exceeded due to a fault condition the device will automatically shut down. the thermal shutdown threshold is approximately 170 c.when the device cools to a temperature below the thermal threshold it will power back up automatically. if the fault persists the part will continue to go in and out of thermal shutdown which can be observed as an oscillation on tip or ring. programming power denial will shut down the device and stop the self cooling cycle. battery switching overview the integrated battery switch selects between high battery and low battery operation. the battery switch is controlled with the logic input bsel. when bsel is a logic high, the high battery (v bh ) is selected. a logic low will enable the low battery (v bl ). all operating modes of the slic will function from high or low battery, but it is strongly recommended forward loop back be enabled only with the low battery. functionality the logic control is independent of the operating mode decode. independent logic control provides the most flexibility and will support all application configurations. when changing device operating states, battery switching should occur simultaneously with or prior to changing the operating mode. in most cases, this will minimize overall power dissipation and prevent glitches on the det output. the only external component required to support the battery switch is a diode in series with the v bh supply lead. in the event that high battery is removed, the diode allows the device to transition to low battery operation. low battery operation all off hook operating conditions should use the low battery to minimize power dissipation. a typical low battery operating voltage for the slic is -24v, however this may be increased to support longer loop lengths or high loop current requirements. standby conditions may also operate from the low battery if mtu compliance is not required, further reducing standby power dissipation. high battery operation other than ringing, the high battery should be used for standby conditions which must provide mtu compliance. during standby operation the power consumption is typically 85mw with -100v battery. if ringing requirements do not require full 100v operation, then a lower battery will result in lower standby power. high voltage decoupling the 100v rating of the slic dictates a capacitor of higher voltage rating be used for decoupling. suggested decoupling values for all device pins are 0.1 f. if the protection scheme shown in figure 15 is implemented the v bh decoupling capacitor should be increased to 0.47uf. this is done to minimize the turn-on time of the battrax device during negative surge transients. standard surface mount ceramic capacitors are rated at 100v. for applications driven by low cost and small size, the decoupling scheme shown in figure 10 could be implemented. it is important to place an external diode between the v bh pin and the decoupling capacitor. connecting the decoupling capacitor directly to the v bh pin will degrade the reliability of the device. refer to figure 15 for the proper arrangement. this applies to both single and stacked and decoupling schemes. if v bl and v bh are tied together the battery switch function is overridden. in this case the external diode is not needed and the decoupling capacitor may be attached directly to v bh pin. v bh v bl 0.22 0.22 ISL5586 figure 10. alternate decoupling scheme figure 11. impedance synthesis tip ring + - -in v fb v zo r f r r + - + - + - 1:1 20 20 3r 4r 4r 4r 4r 3r 8k r s c fb t a v sa il v tr + - v 2w ISL5586
14 impedance and gain derivations the feedback mechanism for monitoring the ac portion of the loop current consists of two ampli?rs, the sense ampli?r (sa) and the transmit ampli?r (ta). the ac feedback signal is used for impedance synthesis. a detailed model of the ac feed back loop is provided below impedance programming resistor derivation the gain of the transmit ampli?r, set by r s , determines the programmed resistance of the slic. for complex line terminations r s is replaced with a complex network z s (figure 1). the capacitor c fb blocks the dc component of the loop current. figure 11 illustrates the impedance synthesis loop. note that the ground symbols shown in figures 11 through 14 represent ac grounds, not necessarily actual dc potentials. the receiver block provides a single-ended to differential conversion with a voltage gain of 2. the voltage at tip and ring due to the feedback from v zo is shown in equation 35. the feedback ampli?r (ta) provides the programmable gain required for impedance synthesis to the receiver block. the output voltage (v zo ) is a function of the sense ampli?r output voltage and the gain of the feedback ampli?r, which can be substituted for v zo . the sense ampli?r shown in figure 11 is con?ured as a 4 input differential ampli?r with a gain of 3/4. the output voltage, v sa , is a function of the voltage across the tip and ring sense resistors (20 ? each) which can also be expressed in terms of loop current. substituting equation 37 into equation 35 and rearranging terms yields z 0 , the slics synthesized 2-wire impedance. rearranging and solving for r s , equation 39 shows the relationship between the impedance programming resistor and the programmed impedance. 4-wire to 2-wire gain the 4-wire to 2-wire gain is de?ed as the gain from the differential receive input to the 2-wire load z l . the gain is a function of the terminating impedance, synthesized impedance and protection resistors and is illustrated in figure 12. the input current to the receiver block irx4w comes from the difference of the v rx input current and the v zo feedback current. this current is fed to the tip and ring ampli?rs and yields the relationship shown in equation 40. the voltage v zo, is a function of the sense ampli?r output voltage v sa. v sa can be expressed in terms of loop current as shown in equation 42. substituting equation 42 into equation 41 gives equation 43. the v z0 term in equation 40 can now be replaced by equation 43 yielding equation 44. a loop equation can be derived for the 2-wire side that replaces v tr as shown in the equation below. expressing il in terms of v 2w /z l , rearranging, and solving for v 2w yields the relationship between the 2-wire voltage and the output of the receive ampli?r. the differential voice input is con?ured for a gain of 1.4. the relationship between v rx and the voice input is shown in equation 47. substituting for v rx , the 4-2-wire gain is shown in equation 48. note that the differential voice input is outside the impedance synthesis loop, so the gain of the receive ampli?r has no effect on the slics impedance. when the combination of the device source impedance and the protection resistors equal the terminating impedance, the receive gain equals 2.92db and is inverted with respect to the 4-wire input. 2-wire to 4-wire gain the 2-wire to 4-wire gain (g 24 ) is defined as the gain from the tip and ring terminals (v tr ) to the v tx differential output. vtr 2 v zo = (eq. 35) vtr 2 v sa r s 8k ? ------------ ?? ?? = (eq. 36) v sa 220il 34 ) ? ( = (eq. 37) z 0 v tr il ----------- 420il 3 4 -- - r s 8k ? ------------ 60 r s 8k ? ------------ == = (eq. 38) r s 133.3 z 0 = (eq. 39) v tr 2v rx v zo () = (eq. 40) v z0 v sa r s 8k ? ------------ = (eq. 41) v sa il 2 20 3 4 -- - = (eq. 42) v z0 il 2 20 3 4 -- - r s 8k ? ------------ = (eq. 43) v tr 2v rx 2il220 3 4 -- - ?? ?? r s 8k ? ------------ ?? ?? = (eq. 44) v 2w il 2r p + 2v rx il 4 20 3 4 -- - ?? ?? r s 8k ? ------------ ?? ?? = (eq. 45) v 2w 2v rx z l z l z 0 2r p ++ ------------------------------------- - ?? ?? ?? = (eq. 46) v rx 1.4 v rxp v rxm () 1.4 v rx4w == (eq. 47) v 2w v rx4w -------------------- 2.8 z l z o +2r p +z l ----------------------------------------- - ?? ?? ?? = (eq. 48) ISL5586
15 note that in figure 13, v tr is referenced on the line side of the protection resistors. on the 2-wire side, solving for il in terms of v in gives equation 49. equations 50 and 51 show the relationship of v in to the outputs of the sense ampli?r (v sa ) and the feedback ampli?r (v z0 ) respectively. simplifying equation 51 in terms of z 0 gives the following equation. the resulting differential output voltage v tx4w , is shown in equation 53. note that the gain from v z0 to the differential output is outside the impedance synthesis loop and will have no effect on the slics programmed impedance. substituting equation 53 into equation 52 and rearranging terms gives the gain from the 2-wire source (v in ) to the differential output of the transmit ampli?r. if the combination of the protection resistors and the programmed impedance of the slic are equal to z l the voltage v tr will be 1/2 v in . the 2-wire to 4-wire gain is de?ed by equation 55. 4-wire to 4-wire gain the 4-wire to 4-wire gain is de?ed in equation 56 and is illustrated in figure 14.the ?st term is identical to equation 48. the second term is derived in a similar manner as the 2-wire to 4-wire gain starting with equation 57. moving around the loop from the 2-wire side to the 4-wire output we solve for v sa and v zo . the relationship between v z0 and the 4-wire output is shown in equation 53. substituting equation 59 into equation 53 yields equation 60, the second term in equation 56. figure 12. schematic for 4-wire to 2-wire gain derivation irx4w tip ring -in v zo 200k + - + - + - 1:1 20 20 3r 4r 4r 4r 4r 3r 8k r s c fb t a v sa i l v tr + - v rxm v rxp v rx4w 1.4r r r 1.4r v 2w r p r p v fb z l v rx + - 200k 200k 200k iz0 + - + - il v in z l z + 0 2r p + ------------------------------------- - ?? ?? ?? = (eq. 49) v sa v in z l z + 0 2r p + ------------------------------------- - ?? ?? ?? 220 3 4 -- - ?? ?? = (eq. 50) v z0 v in z l z + 0 2r p + ------------------------------------- - ?? ?? ?? 220 3 4 -- - ?? ?? r s 8k ? ------------ = (eq. 51) v z0 v in z l z + 0 2r p + ------------------------------------- - ?? ?? ?? z 0 2 ------ = (eq. 52) v tx4w v txp v txm v z0 v ( z0 ) 2v z0 = = = (eq. 53) v tx4w v in ------------------- - z 0 z l z + 0 2r p + ------------------------------------- - ?? ?? ?? = (eq. 54) v tx4w v tr ------------------- - 2z 0 z l z + 0 2r p + ------------------------------------- - ?? ?? ?? = (eq. 55) v tx4w v rx4w -------------------- v 2w v rx4w -------------------- v tx4w v 2w ------------------- - = (eq. 56) v 2w il z l = (eq. 57) v sa i l220 3 4 -- - v 2w z l ------------ 40 3 4 -- - = = (eq. 58) v z0 v 2w z l ------------ r s 8k ? ------------ ?? ?? 40 3 4 -- - v 2w z l ------------ z 0 2 ------ == (eq. 59) v tx4w v 2w ------------------- - z 0 z l ------ = (eq. 60) ISL5586
16 equations 48 and 60 can be combined to re-write the 4-wire to 4-wire gain equation. simplifying the above yields the 4-wire to 4-wire gain. v tx4w v rx4w -------------------- 2.8 z l z o +2r p +z l ----------------------------------------- - ?? ?? ?? z 0 z l ------ = (eq. 61) v tx4w v rx4w -------------------- 2.8 z 0 z o +2r p +z l ----------------------------------------- - ?? ?? ?? = (eq. 62) figure 13. schematic for 2-wire to 4-wire gain derivation + - -in v fb v rx v zo 200k 200k + - + - + - 1:1 20 20 3r 4r 4r 4r 4r 3r 8k r s c fb t a v sa + - v rxp v rxm v txp v txm r r r r + - r p1 r p2 v tr z l v in i l v tx4w + - 200k 200k 1.4r 1.4r tip ring + - figure 14. schematic for 4-wire to 4-wire gain derivation t r + - -in v fb v rx v zo + - + - + - 1:1 20 20 3r 4r 4r 4r 4r 3r 8k r s c fb t a v sa + - + - v rxp v rxm v txp v txm r r r r r p1 r p2 z l il v tx4w - + v 2w + - + - v rx4w 200k 200k 200k 200k 1.4r 1.4r pin descriptions plcc symbol description 1 tip tip power amplifier output. 2 bgnd battery ground - to be connected to zero potential. all loop current and longitudinal current flow from this ground. internally separate from agnd and sgnd but should be connected to the same potential as agnd & sgnd. 3v bl low battery supply connection. 4v bh high battery supply connection. 5 bsel selects between high and low battery, with a logic ??selecting the high battery and logic ??the low battery. ISL5586
17 6 f2 ttl mode control input - msb. 7 f1 ttl mode control input. 8 f0 ttl mode control input - lsb. 9 det detector output - this ttl output provides on-hook/off-hook status of the loop based upon the selected operating mode. the detected output will either be switch hook or ring trip. 10 v rsp non-inverting ringing signal input - analog input for driving 2-wire interface while in ring mode. 11 v rsm inverting ringing signal input - analog input for driving 2-wire interface while in ring mode. 12 v txp transmit output voltage - ac couples to codec. 13 v txm transmit output voltage - ac couples to codec. 14 agnd analog ground reference. this pin should be externally connected to bgnd. 15 pol an external capacitor on this pin sets the polarity reversal time. 16 v rxp non-inverting analog receive voltage - 4-wire analog audio input voltage. 17 v rxm inverting analog receive voltage - 4-wire analog audio input voltage. 18 v zo connection terminal for impedance matching programming resistor 19 -in connection terminal for high pass filter capacitor and impedance matching components. 20 v fb connection terminal for high pass filter capacitor and impedance matching components. 21 tl transient current limit programming resistor connection terminal. 22 v cc positive voltage power supply, +5v +/-5%. 23 c dcp dc biasing filter capacitor - positive terminal. 24 c dcm dc biasing filter capacitor - negative terminal. 25 rtd ring trip filter network connection terminal. 26 i lim loop current limit programming resistor connection terminal. 27 rd switch hook detection threshold programming resistor connection terminal. 28 ring ring power amplifier output. pin descriptions (continued) plcc symbol description ISL5586
18 basic application circuit figure 15. ISL5586 basic application circuit v rxp v txp tip vfb bgnd agnd ring v zo -in bsel rd rtd cdcm ilim f2 f1 f0 det pol r il c fb r s r sh c rt r rt c pol c dc r p1 v cc v bl v bh c ps1 c ps3 c ps2 tl r tl r p2 c sh v txm v rsp v rsm v rxm r p c p cdcp d 1 ISL5586 b1100cc b1100cc f1250t f1250t 3 3 2 2 1 1 note: cps1 should be located as close as possible to the b1100cc to minimize turn-on time. less than 2 inches is recommended. c txm c txp table 2. basic application circuit component list component value tolerance rating u1 - ringing slic ISL5586 n/a n/a r tl 17.8k ? 1% 0.1w r rt 22.1k ? 1% 0.1w r sh 40k ? 1% 0.1w r il 71.5k ? 1% 0.1w r s 66.5k ? 1% 0.1w r p 0 ? 1% 0.1w c p not populated 20% 10v c rt , c pol ,c sh , c txp , c txm 0.47 f 20% 10v cfb 1.0 f 20% 10v c dc 4.7 f 20% 10v c ps1 0.47 f 20% >100v c ps2 , c ps3 0.1 f 20% 100v d 1 1n400x type with breakdown > 100v. d 2, d 3 1n4935 type r p1 , r p2 protection resistor values are application dependent and will be determined by protection requirements. standard applications will use 49 ? per side. design parameters : ring trip threshold = 81ma peak , switch hook threshold = 15ma, loop current limit = 24.6ma, synthesize device impedance = (3*66.5k ?) /400 = 498.8 ? , protection resistors = 50 ? , impedance across tip and ring terminals = 599 ? . transient current limit = 100ma. ISL5586
19 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (321) 724-7000 fax: (321) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil ltd. 8f-2, 96, sec. 1, chien-kuo north, taipei, taiwan 104 republic of china tel: 886-2-2515-8508 fax: 886-2-2515-8369 ISL5586 plastic leaded chip carrier packages (plcc) notes: 1. controlling dimension: inch. converted millimeter dimensions are not necessarily exact. 2. dimensions and tolerancing per ansi y14.5m-1982. 3. dimensions d1 and e1 do not include mold protrusions. allowable mold protrusion is 0.010 inch (0.25mm) per side. dimensions d1 and e1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. to be measured at seating plane contact point. 5. centerline to be determined where center leads exit plastic body. 6. ??is the number of terminal positions. -c- a1 a seating plane 0.020 (0.51) min view ? d2/e2 0.025 (0.64) 0.045 (1.14) r 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) tp e e1 0.042 (1.07) 0.048 (1.22) pin (1) identifier c l d1 d 0.020 (0.51) max 3 plcs 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) min 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) min view ??typ. 0.004 (0.10) c -c- d2/e2 c l n28.45 (jedec ms-018ab issue a) 28 lead plastic leaded chip carrier package symbol inches millimeters notes min max min max a 0.165 0.180 4.20 4.57 - a1 0.090 0.120 2.29 3.04 - d 0.485 0.495 12.32 12.57 - d1 0.450 0.456 11.43 11.58 3 d2 0.191 0.219 4.86 5.56 4, 5 e 0.485 0.495 12.32 12.57 - e1 0.450 0.456 11.43 11.58 3 e2 0.191 0.219 4.86 5.56 4, 5 n28 286 rev. 2 11/97

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